1. Field of the Invention
The present invention relates to a microprocessor, and more specifically to a status notice of a microprocessor having an instruction processing function for executing a freezing or a temporary halt in the course of the execution of an instruction.
2. Description of Related Art
An instruction set of a microprocessor may contain an instruction for interrupting or temporarily stopping the execution of the instruction in order to prevent the execution of processing of subsequent instructions. For example, this instruction can be exemplified by a HALT instruction in a 32-bit microprocessor i80386 of Intel Corp. This HALT instruction has a function of preventing the execution of instructions described after the HALT instruction and holding the internal status of the microprocessor. This condition is called a "halt condition". The halt condition is released by activation of an external terminal for a reset, a non-maskable interrupt or a maskable interrupt.
When a reset request is activated, the microprocessor is initialized, similarly to the case in which an instruction other than the HALT instruction is being executed. On the other hand, when a non-maskable interrupt request or a maskable interrupt request is activated, an interrupt processing is executed, similarly to the case in which an instruction other than the HALT instruction is executed. The interrupt processing is generally acknowledged at the completion of the execution of the instruction. However, the interrupt request is immediately acknowledged when the microprocessor is in the halt condition.
In the microprocessor i80386 mentioned above, status of register resources (PC: Program Counter, CS: Code Segment register, PSW: Program Status Word) are automatically saved in a stack area within a memory when the interrupt is acknowledged. They are saved in order to restart, after the completion of the interrupt processing, the execution of the interrupted instruction sequence from an instruction located at an address arranged next to the address where the HALT instruction has been arranged.
The halt/interrupt instruction typified by the HALT instruction is used for the following purposes:
1) Stop of the microprocessor at the completion of the instruction execution processing.
2) Waiting for a real time processing started by an interrupt request.
3) Debugging by substitution of an instruction in a program.
When a halt/interrupt instruction is executed, there occurs no external change in the status of terminals such as a terminal for starting a bus cycle. Thus, it is necessary to detect at which position of the instruction sequence the status had changed to the halt condition in the course of debugging of the program.
In the microprocessor i80386 as mentioned above, the transition to the halt condition can be recognized by starting a special bus cycle called "HALT Indication Cycle". The halt indication cycle has a particular value ("1011.sub.b " where the suffix "b" means a binary notation) for a status signal (BE#3-BE#0) for recognizing the kind of the bus cycle, in order to distinguish it from the bus cycles for access to the memory and an I/O (input/output) unit.
The bus cycle is generally divided into two kinds: a write type for driving a data bus terminal by the microprocessor and a read type for maintaining the data bus terminal in a high impedance condition (Hi-Z). The halt indication cycle of the microprocessor i80386 is the write type bus cycle in which all address bus terminals (A.sub.31 -A.sub.2) are driven to "0", and an indefinite value is driven to data bus terminals (D.sub.31 -D.sub.0).
Among other methods of informing of the transition to the halt condition, there is another method used in the 16-bit microprocessor MC68000 of Motorola Inc. The microprocessor MC68000 comprises a terminal HALT used only for indicating the halt condition. This terminal is activated when the microprocessor is transited to the HALT condition. The terminal HALT is an input/output terminal which not only indicates the halt condition as the output terminal, but also it can be activated as the input terminal from the external when the microprocessor is in a condition other than the halt condition, so that the microprocessor is forcibly transited temporarily to the halt condition.
In this case, the special bus cycle for the indication of the halt condition is not started.
In the case of debugging a program including a halt/interrupt instruction, it is necessary to know the register resource or the internal status of the microprocessor when the halt/interrupt instruction has been executed.
In the debugging, the most important register resource is a program counter representing until where the instruction sequence has been processed. It is possible to know the flow of the program execution in some degree by observing the status of the address bus terminal outputted in the course of the memory read cycle (fetch cycle) for fetching an instruction.
It is also possible to guess the range of the address in which the halt/interrupt instruction has been executed, by storing the status of the address bus terminal in the fetch cycle issued just before the start of the halt display cycle or the activation of the terminal HALT.
However, from the status of the address bus terminal in the course of the fetch cycle, it is not possible to correctly identify the address where the halt/interrupt instruction has been executed, in the following situations:
(1) In the case that the address bus terminal is insufficient for the identification of the byte address: PA0 (2) In the case that the microprocessor executes a pipelined processing:
In the microprocessor i80386 mentioned above, the program counter has a width of 32 bits, while the address bus terminal has a width of 30 bits (A.sub.31 -A.sub.2) to identify the word address (32-bit unit data). Thus, it is impossible to know at which byte within the word address is positioned the HALT instruction which had caused the transition to the halt condition.
In order to improve the instruction executing performance, a pipelined processing is adopted in which one instruction is divided into a plurality of processings (stages) and the plurality of processings are executed at the same time. Typical pipeline stages are composed of (1) instruction code fetch, (2) instruction decode, (3) calculation of the effective address of the memory operand, (4) address translation from a virtual address to a physical address (in the case of adopting the virtual memory method), (5) reading of the operand, (6) execution of the instruction and (7) store of the result.
In the case that a large number of pipeline stages are adopted in this way, the "instruction code fetch" precedes the "store of the result" (which is positioned at the end of a series of execution stages) by several instructions. Thus, when the issue of the halt indication cycle or the activation of the terminal HALT is detected from the external, the address indicated in the just preceding fetch cycle has preceded the address of the instruction transited to the halt condition, and therefore, it is necessary to correct the address.
However, it is not possible to identify the number of the instructions by which the fetch cycle precedes, because the processing times of the respective pipelined stages is different dependent upon instructions. (3) In the case that instruction codes are stored in a cache memory:
In the case of the microprocessor having an instruction code cache memory for aching instruction codes (for example, the microprocessor i80386), if the instruction sequence is stored in the instruction code cache memory (in the case of hitting), an instruction is not fetched from the external memory (the fetch cycle is not staffed), and the instruction code is supplied from the instruction code cache memory.
Thus, in the case that it is transited to the halt condition when the instruction code cache memory is hit, the just preceding fetch cycle has a completely meaningless value in the address detection.